Tips and quirks

TRUE and FALSE in design constraint properties

By default 'TRUE', 'true', 'True' are interpreted by YAML as boolean and then printed to the file as 'True' string. In .xdc file we want 'TRUE' string so double qoutes " are needed. Not sure which EDA tools can handle correctly 'True' or 'true' strings, but Xilinx Vivado can’t. The same applies to the "FALSE".

_default_:
  set_property:
    IOSTANDARD: LVDS_33
    # Use "TRUE" or "FALSE" strings for boolean properties.
    DIFF_TERM: "TRUE"

Net names on schematics

It is always preferred to put numbers at the end of net names in the board schematics files. This is because in case of HDL, the array indexes are always at the end. For example, following declaration:

_default_:
  regex:

foo_[pn]_\[[0-4]\]:
  end: bar_[0-4]_[pn]

leads to improper assignment as order in natural sorting is different than what user expects. This is because [0-4] is before [pn] in bar_[0-4]_[pn].

Instead user needs to write it in a much more verbose way:

_default_:
  regex:

foo_[pn]_\[0\]:
  end: bar_0_[pn]

foo_[pn]_\[1\]:
  end: bar_1_[pn]

foo_[pn]_\[2\]:
  end: bar_2_[pn]

foo_[pn]_\[3\]:
  end: bar_3_[pn]

foo_[pn]_\[4\]:
  end: bar_4_[pn]

Such verbosity could be avoided if the nets on the schematic were named in the following way bar_[pn]_[0-4] instead of bar_[0-4]_[pn]. Then following declaration

_default_:
  regex:

foo_[pn]_\[[0-4]\]:
  end: bar_[pn]_[0-4]

would work as user expects.